The present invention relates to a multi-computer system having a plurality of data processors and at least one I/O device which is commonly accessible by the data processors, and more particularly to a multi-computer system with hierarchical serial bus loops coupled by interbus linkage devices.
In order to enhance the reliability of a system, a multi-computer system has been proposed in which a plurality of data processors (hereinafter referred to as CPU's) and input/output devices (hereinafter referred to as I/O devices) are connected to the system so that when a CPU or I/O device fails, another CPU or I/O device backs up the failed one. Such a system needs an I/O device which can be commonly accessed by a plurality of CPU's. An example of a known approach to this problem is to connect the CPU's respectively to exclusive buses with the I/O devices which are to be exclusively accessed by the respective CPU's being connected to these exclusive buses, to connect the I/O devices which are to be commonly accessed by the respective CPU's to a common bus which is to be shared by the CPU's, and to interconnect the exclusive buses and the common bus through a switching mechanism (for example, see Japanese Patent Publication No. 55-4299 of the present assignee, entitled "A multi-dimension addressing system in a multi-computer system). In this example, one of the exclusive buses is selectively connected to the common bus by the switching mechanism so that the CPU connected to the selected exclusive bus can access the I/O devices connected to the common bus. Since the switching mechanism connects one of the exclusive buses to the common bus upon request by the CPU, the CPU's are commonly accessible by an I/O device connected to the common bus or vice versa. If a CPU which is carrying out a job of a commonly accessible I/O device fails, another CPU can be connected by the switching mechanism so that the substituted CPU continues to carry out the job.
According to such a multi-computer system, the system does not go down even if one of the exclusive buses fails because the exclusive buses operate independently to each other. Also, the processing ability is enhanced by the independency of the operation of the respective buses.
However, in a system with parallel interface type I/O operation in which data is transferred in parallel through parallel signal lines connecting the CPU's and the I/O devices, the number of signal lines increases extremely, especially in a large scale system.
On the other hand, a data highway system in which a single serial interface line is looped has been proposed (for example, see U.S. Pat. No. 4,002,847). When a plurality of CPU's and a plurality of I/O devices are connected to the same serial bus loop, any CPU can access any I/O device and hence the back-up for a failed CPU can be readily carried out. However, if the loop fails at some location in such a system, the entire system goes down and hence the advantage of high reliability in the multi-computer system is lost. The reliability may be enhanced by providing double or triple loops, but the processing efficiency is reduced. The processing efficiency is also reduced because all of the CPU's and the I/O devices are connected to a single loop.